Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to an embedded package structure having power overlay (POL) interconnects that form all electrical and thermal interconnections in the package.
Surface-mount technology is a method for constructing electronic circuits in which surface mount components or packages are mounted directly onto the surface of printed circuit boards (PCBs) or other similar external circuits. In the industry, surface-mount technology has replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board.
One common technique for surface-mounting a semiconductor device (or a multi-chip module) is to provide a package structure in which the device/module is encapsulated within an embedding compound. The package manufacturing process begins with placement of one or more semiconductor devices onto a dielectric layer by way of an adhesive, with the dielectric layer covering the active side of each semiconductor device. Metal interconnects are then electroplated onto the dielectric layer to form a direct metallic connection to the semiconductor device(s). The interconnects may be routed through additional laminate re-distribution layers, if desired, and an input/output system is provided to enable surface mounting of the package onto the PCB or external circuit. An embedding compound is applied about the semiconductor device(s) to encapsulate the semiconductor device(s) therein.
In an embodiment where the semiconductor device is a high voltage power semiconductor device, the power semiconductor device can be surface mounted to an external circuit by way of a power overlay (POL) packaging and interconnect system, with the POL package also providing a way to remove the heat generated by the device and protect the device from the external environment. A standard POL package manufacturing process typically begins with placement of one or more semiconductor devices onto a dielectric layer by way of an adhesive and drilling via holes though the dielectric to the devices. Metal interconnects (e.g., copper interconnects) are then electroplated onto the dielectric layer and into the vias to form a direct metallic connection to the semiconductor device(s), so as to form a sub-module. The metal interconnects may be in the form of a low profile, planar interconnect structure that provides for formation of an input/output (I/O) system to and from the semiconductor device(s). The POL sub-module is then soldered to a ceramic substrate (Alumina with DBC, AlN with AMB Cu, etc.) using soldered interconnection for electrical and thermal connectivity. The gaps around the semiconductor device(s) between the dielectric layer and the ceramic substrate are then filled using a dielectric organic material using either capillary flow (capillary underfill), no-flow underfill or injection molding (molding compounds) to form the POL package.
With regard to the packaging manufacturing processes set forth above that embed semiconductor devices, modules, and/or power devices, it is recognized, that numerous drawbacks are associated therewith. For example, the encapsulants and embedding compounds that are generally used have limited reliability when moisture sensitivity level (MSL)-qualification is required, due to their poor fracture toughness and high moisture uptake. Additionally, the encapsulants/embedding compounds typically used can be expensive to procure and slow and time consuming to apply.
Furthermore, and with particular regard to packaging power devices/modules, the soldering operation typically employed for electrically and thermally connecting the POL sub-module to the ceramic substrate can be costly and time consuming, with the additional temperature excursion required by soldering also adversely affecting module reliability. Still further, the inclusion of the ceramic substrate in the POL package places limits on an achievable reduction in size and thickness of the POL package (i.e., miniaturization) due to the size/thickness of the ceramic substrate. Thus, the desire to miniaturize modules to reduce system weight, cost and size while increasing electrical, thermal and mechanical performance is restrained by existing POL package structures.
Therefore, it would be desirable to provide a semiconductor device package structure that is surface mount compatible, and has a very low thickness. It would further be desirable for such a package structure to be manufactured at a reduced cost but increase system-level performance.